/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (C) 2020 Nuvoton Technology Corp.
 *
 */

#ifndef __NUVOTON_MA35D1_RESET_H__
#define __NUVOTON_MA35D1_RESET_H__

#define MA35D1_RESET_CHIP		0
#define MA35D1_RESET_CA35CR0		1
#define MA35D1_RESET_CA35CR1		2
#define MA35D1_RESET_CM4		3
#define MA35D1_RESET_PDMA0		4
#define MA35D1_RESET_PDMA1		5
#define MA35D1_RESET_PDMA2		6
#define MA35D1_RESET_PDMA3		7
#define MA35D1_RESET_DISP		9
#define MA35D1_RESET_VCAP0		10
#define MA35D1_RESET_VCAP1		11
#define MA35D1_RESET_GFX		12
#define MA35D1_RESET_VDEC		13
#define MA35D1_RESET_WHC0		14
#define MA35D1_RESET_WHC1		15
#define MA35D1_RESET_GMAC0		16
#define MA35D1_RESET_GMAC1		17
#define MA35D1_RESET_HWSEM		18
#define MA35D1_RESET_EBI		19
#define MA35D1_RESET_HSUSBH0		20
#define MA35D1_RESET_HSUSBH1		21
#define MA35D1_RESET_HSUSBD		22
#define MA35D1_RESET_USBHL		23
#define MA35D1_RESET_SDH0		24
#define MA35D1_RESET_SDH1		25
#define MA35D1_RESET_NAND		26
#define MA35D1_RESET_GPIO		27
#define MA35D1_RESET_MCTLP		28
#define MA35D1_RESET_MCTLC		29
#define MA35D1_RESET_DDRPUB		30
#define MA35D1_RESET_TMR0		34
#define MA35D1_RESET_TMR1		35
#define MA35D1_RESET_TMR2		36
#define MA35D1_RESET_TMR3		37
#define MA35D1_RESET_I2C0		40
#define MA35D1_RESET_I2C1		41
#define MA35D1_RESET_I2C2		42
#define MA35D1_RESET_I2C3		43
#define MA35D1_RESET_QSPI0		44
#define MA35D1_RESET_SPI0		45
#define MA35D1_RESET_SPI1		46
#define MA35D1_RESET_SPI2		47
#define MA35D1_RESET_UART0		48
#define MA35D1_RESET_UART1		49
#define MA35D1_RESET_UART2		50
#define MA35D1_RESET_UAER3		51
#define MA35D1_RESET_UART4		52
#define MA35D1_RESET_UART5		53
#define MA35D1_RESET_UART6		54
#define MA35D1_RESET_UART7		55
#define MA35D1_RESET_CANFD0		56
#define MA35D1_RESET_CANFD1		57
#define MA35D1_RESET_EADC0		60
#define MA35D1_RESET_I2S0		61
#define MA35D1_RESET_SC0		64
#define MA35D1_RESET_SC1		65
#define MA35D1_RESET_QSPI1		68
#define MA35D1_RESET_SPI3		70
#define MA35D1_RESET_EPWM0		80
#define MA35D1_RESET_EPWM1		81
#define MA35D1_RESET_QEI0		86
#define MA35D1_RESET_QEI1		87
#define MA35D1_RESET_ECAP0		90
#define MA35D1_RESET_ECAP1		91
#define MA35D1_RESET_CANFD2		92
#define MA35D1_RESET_ADC0		95
#define MA35D1_RESET_TMR4		96
#define MA35D1_RESET_TMR5		97
#define MA35D1_RESET_TMR6		98
#define MA35D1_RESET_TMR7		99
#define MA35D1_RESET_TMR8		100
#define MA35D1_RESET_TMR9		101
#define MA35D1_RESET_TMR10		102
#define MA35D1_RESET_TMR11		103
#define MA35D1_RESET_UART8		104
#define MA35D1_RESET_UART9		105
#define MA35D1_RESET_UART10		106
#define MA35D1_RESET_UART11		107
#define MA35D1_RESET_UART12		108
#define MA35D1_RESET_UART13		109
#define MA35D1_RESET_UART14		110
#define MA35D1_RESET_UART15		111
#define MA35D1_RESET_UART16		112
#define MA35D1_RESET_I2S1		113
#define MA35D1_RESET_I2C4		114
#define MA35D1_RESET_I2C5		115
#define MA35D1_RESET_EPWM2		116
#define MA35D1_RESET_ECAP2		117
#define MA35D1_RESET_QEI2		118
#define MA35D1_RESET_CANFD3		119
#define MA35D1_RESET_KPI		120
#define MA35D1_RESET_GIC		124
#define MA35D1_RESET_SSMCC		126
#define MA35D1_RESET_SSPCC		127

#define MA35D1_RESET_COUNT		128

#endif	//__NUVOTON_MA35D1_RESET_H__
